computer architecture nptel assignment answers 2023
The ARM instruction tst r1, r2 sets the CPSR flags after computing which condition?
r1 AND r2
r1 OR r2
r1 XOR r2
r1 ADD r2
The ARM instruction tst r1, r2 sets the CPSR (Current Program Status Register) flags after computing the condition r1 AND r2. The tst instruction performs a bitwise AND operation between the values in registers r1 and r2, and the result of this operation determines the state of the CPSR flags.
In the SimpleRisc ISA, register ____ saves a pointer to the top of the stack.
r14
r13
r12
r15
In the SimpleRisc ISA, register r13 (also commonly denoted as sp for "stack pointer") is used to save a pointer to the top of the stack. This register is used for managing the stack in function calls and memory allocation operations.
Which of the following problems are solved by the stack?
Space problem
Overwrite problem
Management of activation blocks
All of the options
All of the options mentioned – Space problem, Overwrite problem, and Management of activation blocks – are problems that are solved by the stack.
Space problem: The stack provides a way to efficiently manage and allocate memory for temporary data and function call parameters. It helps address the problem of limited memory space by providing a compact and organized way to allocate and deallocate memory as needed.
Overwrite problem: The stack ensures that data is stored in a controlled manner, preventing overwrite problems that can occur when multiple functions or processes use shared memory locations. Each function call or activation creates a separate stack frame, which helps isolate data and prevents overwrite issues.
Management of activation blocks: The stack is used to manage activation records (also known as stack frames) during function calls. Each function call creates a new activation record on the stack, which stores information like local variables, return addresses, and other context needed for the function execution. The stack's LIFO (Last-In-First-Out) nature ensures that activation records are managed in a structured and efficient manner.
So, the correct answer is: All of the options.
computer architecture nptel week 3 assignment answers
Consider the following ARM assembly code sequence.
mov r0, #8
mov r1, #1
mul r4, r0, r0
mla r3, r4, r0, r1
What is the final value of r3?
82 + 1
83 + 1
82 + 8
83
Let's break down the ARM assembly code sequence step by step:
mov r0, #8 - This moves the immediate value 8 into register r0.
mov r1, #1 - This moves the immediate value 1 into register r1.
mul r4, r0, r0 - This multiplies the values in registers r0 and r0 (both containing 8) and stores the result in register r4. So, r4 will hold the value 8 * 8 = 64.
mla r3, r4, r0, r1 - This performs a multiply-accumulate operation. It multiplies the values in registers r4 (64) and r0 (8), and then adds the value in register r1 (1). The result is stored in register r3.
The calculation is: 64 * 8 + 1 = 513.
So, the final value of r3 is 513.
computer architecture nptel assignment answers
Which of the following ARM assembly instructions computes r1= r2 + r3*4 ?
add r1, r2, r3, asl #2
add r1, r2, r3, asr #2
add r1, r2, r3, lsr #2
add r1, r2, r3, lsl #2
The ARM assembly instruction that computes r1 = r2 + r3 * 4 is:
add r1, r2, r3, lsl #2
In this instruction, lsl #2 means "logical shift left by 2 bits," which effectively multiplies the value in register r3 by 4 before adding it to the value in register r2, and the result is stored in register r1.
Which of the following instructions is a conditional branch instruction?
call
bgt
ret
b
The conditional branch instruction among the options provided is:
assembly
Copy code
bgt
The bgt instruction stands for "branch if greater than" and is used for conditional branching based on the comparison of two values. It checks the condition of whether the preceding comparison result indicates that the source value is greater than the destination value. If the condition is met, the branch is taken; otherwise, execution continues with the next instruction.
computer architecture nptel course
In an ARM Machine, which of the following expressions is computed by the instruction “bic r1, r2, r3”?
r1 ← ~r2 OR (r3)
r1 ← r2 OR (~r3)
r1 ← ~r2 AND (r3)
r1 ← r2 AND (~r3)
The expression computed by the ARM instruction "bic r1, r2, r3" is:
assembly
Copy code
r1 ← r2 AND (~r3)
The bic (Bit Clear) instruction performs a bitwise AND operation between the value in register r2 and the bitwise complement (NOT) of the value in register r3. The result is then stored in register r1. This operation effectively clears (sets to 0) the bits in r1 that correspond to the 1 bits in the bitwise complement of r3.
Which of the following instructions is not a 1-address instruction?
call
b
bne
cmp
Among the provided options, the instruction "cmp" is not a 1-address instruction.
call: A "call" instruction is typically used for subroutine calls, where the address of the subroutine is usually specified explicitly or indirectly, and it can involve multiple operands.
b and bne: Both "b" (branch) and "bne" (branch if not equal) are 1-address instructions. They involve a single operand, which is typically the target address for the branch.
cmp: The "cmp" instruction is a 2-address instruction. It is used to compare two values and set the condition flags in the processor's status register based on the result of the comparison. It does not modify any of the operands, so it's not a 1-address instruction.
So, the answer is "cmp".
Which of the following ARM instructions sets the flags of the CPSR registers?
cmn
teq
adds
All of the options
All of the provided options—cmn, teq, and adds—set the flags of the CPSR (Current Program Status Register) registers in ARM instructions.
cmn: The "cmn" instruction performs a bitwise addition of two operands and sets the flags in the CPSR based on the result of the addition.
teq: The "teq" instruction performs a bitwise exclusive OR (XOR) of two operands and sets the flags in the CPSR based on the result of the XOR operation.
adds: The "adds" instruction performs a signed addition of two operands and sets the flags in the CPSR based on the result of the addition.
So, the correct answer is: All of the options.
Consider the following ARM assembly code:
mov r1, #19
add r1, r1, #5
sub r1, r1, #4
What is the final value of register r1?
-20
20
40
-40
Let's break down the ARM assembly code step by step:
mov r1, #19 - This moves the immediate value 19 into register r1.
add r1, r1, #5 - This adds the immediate value 5 to the value in register r1.
sub r1, r1, #4 - This subtracts the immediate value 4 from the value in register r1.
Adding 5 and subtracting 4 from the initial value of 19:
19 + 5 - 4 = 20
So, the final value of register r1 is 20.